The present invention relates to methods and apparatus for controlling static random access memory (SRAM).
SRAM memory cells store data in the form of complementary low voltage and high voltage at opposite sides of the cell. An SRAM, unlike dynamic random access memory (DRAM), maintains the data content of the memory calls as long as power is applied to the cell. DRAM memory cells, on the other hand, are periodically refreshed with the stored data content. An SRAM cell includes a “true” node associated with a bit line of the SRAM memory and a complementary node associated with a complementary bit line of the SRAM memory. When the true node is read as a high voltage, the value of the SRAM memory cell is digital one. If the true node is read as a low voltage, the value of the SRAM memory cell is a digital zero.
During write and read cycles, a conventional SRAM memory system will employ a pre-charge circuit to drive the bit line and the complementary bit line to a power supply voltage of the SRAM memory, Vdd, before data is written to the memory cell. During the time that the data is actually written to the SRAM memory cell, a write buffer drives the bit line and the complementary bit line. Depending on the data being written (logic high or low) the bit line and complementary bit line will experience a full voltage swing between the pre-charge level, Vdd, and a common potential level, usually ground, Vss.
Successive write cycles at a relatively high frequency clock will cause successive full voltage swing on the bit line and complementary bit line. This produces power dissipation in the SRAM memory system. The power dissipation problem becomes significantly worse as the frequency of the clock increases, which is an ongoing circumstance as higher and higher memory performance remains a design goal.
Accordingly, there is a need in the art for a new approach to controlling SRAM memory cells in order to counteract the increase in power dissipation resulting from higher and higher clock frequencies.